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tdt1_2010 [2011/05/13 08:51]
jahre created
tdt1_2010 [2011/05/13 08:52] (current)
jahre
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 +====== TDT1 Multicore Architectures and Chip Multiprocessors - 2010 ======
  
 +**Students**: Angelo Spalluto, Anders Nore, Kjetil Jørgensen, Håkon Karsten Eide, Bahram Najafi Uchevler, Jorge Suárez Cabanas, Peter Hemmen, Thomas Bergheim.
 +
 +**TDT1** is a specialist 5th year course on **multicore architectures and chip multiprocessors**. The course will focus on having an up to date reading list of high quality, but with relatively few meetings. In the startup meeting at 16/9 we found that OK timeslots are Monday 1115-1200, Tuesday 1515-1600, and Thursday 1015-1200 for those lectures that //can// be moved.
 +
 +**Reading list**:
 +  - **[[http://www.idi.ntnu.no/~jahre/jahre-phd-thesis-print.pdf|Managing Shared Resources in Chip Multiprocessor Memory Systems]]**, pages 1-32 of Magnus Jahre's PhD thesis, covered partly by his PhD defense lecture, slides: [[http://research.idi.ntnu.no/multicore/_media/phd-defence.ppsx?id=start&cache=cache|show]], [[http://research.idi.ntnu.no/multicore/_media/phd-defence.pdf?id=start&cache=cache|pdf]].
 +  - **The new [[http://www.hipeac.net/system/files/LR_3910_hipeac_roadmap-2010-v3.pdf|HiPEAC Vision]]** Slides are already available [[http://www.hipeac.net/system/files/hipeacvision.pdf|here]], and they are considered part of the course. **Vision document and slides** available also in course intranet (ITLS). Video available [[http://www.hipeac.net/|here]].
 +  - **ArchExplorer.org: Joint Compiler/Hardware Exploration for Fair Comparison of Architectures**, Veerle Desmet, Sylvain Girbal, and Olivier Temam; INTERACT-13, Workshop on Interaction Between Compilers and Computer Architecture, held in conjunction with HPCA-15, February 15, 2009. (Available through course intranet (ITSL)).
 +  - **[[http://www.jilp.org/dpc/online/papers/02grannaes.pdf|Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables]]**, from [[http://www.jilp.org/dpc/|1st JILP Data Prefetching Championship]]. See also [[http://www.idi.ntnu.no/news/index.php?news=184|IDI news]]
 +  - **[[http://ce.et.tudelft.nl/publicationfiles/1557_68_powerTechReport.pdf|(When) Will CMPs hit the Power Wall?]]**, Cor Meenderinck and Ben Juurlink, Technical Report TUDelft, 2008. 
 +  -  **[[http://www.hppc-workshop.org/HPPC10-Held.pdf|“Single-chip Cloud Computer”, an IA Tera-scale Research Processor]]**, HPPC - 2010 Keynote, by Jim Held, Tera-Scale Computing Research, Intel. 31 aug 2010, Ischia, Italy. [[http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5434077|ISSCC-paper]] (February 2010) (Paper also available in ITSL)
 +  - **[[http://softwarecommunity.intel.com/UserFiles/en-us/File/larrabee_manycore.pdf| Larrabee: A Many-Core x86 Architecture for Visual Computing]]**, Larry Seiler et.al., ACM Transactions on Graphics, Vol. 27, No. 3, August 2008.
 +  - **[[http://www.cs.wisc.edu/multifacet/papers/ieeecomputer08_amdahl_multicore.pdf|Amdahl's Law in the Multicore Era]]**, by Mark D. Hill and Michael R. Marty, IEEE Computer, July 2008. See also the [[http://www.cs.wisc.edu/multifacet/amdahl/|webpage]] including a 52 min you tube video lecture.
 +  - **[[http://www.caviumnetworks.com/pdfFiles/CN68XX_PB%20%20Rev%201.pdf?v=1|Octeon-II multicore processor]]**
 +  - **Introduction to the wire-speed processor and architecture**, IBM J. of Res. & Dev., vol 54, no 1, Jan/Feb 2010. (Available through course intranet (ITSL)).
 +
 +//Questions can be addressed to Lasse Natvig, preferably by E-mail.
 +//
 +
 +{{:tilera_chip.jpg|}}



2011/05/13 08:52, Magnus Jahre