TDT1 Energy Efficient Multicore Computing - 2013, history

The reading list is now final. We had a start-up meeting at September 16th.

The PP4EE seminar at 3 October is part of the course. Videos of most of the presentations are now here. Slides are available from the seminar-page here. The course has a project space under Its'learning. There you find a short specification of which seminar-slides is considered part of the course (relevant for exam).

Meetings 2013 (Paper numbers refer to the list below, Resp. is abbreviation for Responsible for presenting the paper in the meeting). Papers 1, 3 and 15 are self-study papers.

  • Monday 30/9, 15:15-17:00(max) in room 454: Paper 4 (Resp. Håkon Wikene & Matthew) slides, Paper 12 (Resp. Bjørn & Benjamin) slides link, and Paper 13 (Resp. Magnus W and Mayeul) slides
  • Monday 14/10, 15:15-17:00(max) in room 454: Paper 7 (Terje S & Einar Johan) slides, Paper 5 (Resp. Erik L & Jakob K) slides, Paper 11 (Resp. Anders & Sebastian) slides
  • Monday 28/10, 15:15-17:00(max) in room 454: Paper 6 (Resp. Torbjørn & Christer) slidesslides, Paper 8 (Resp. Stian & Terje R.) slides
  • Monday 4/11, 15:15-17:00(max) in room 454: Paper 9 (Resp. Joakim & Håkon A) slides, Paper 10 (Resp. Erik S & Magnus U) slides
  • Monday 11/11, 15:15-17:00(max) in room 454: Paper 2 (Øivind & Eirik M) slides, Paper 14 (Resp. Caroline & Jean Niklas) slides

Reading list:

  1. HiPEAC Roadmap 2013, pdf
  2. GPU Acceleration for FEM-Based Structural Analysis, link, Serban Georgescu, Peter Chow and Hiroshi Okuda, Springer Verlag June 2013.
  3. Green Computing: Saving Energy by Throttling, Simplicity and Parallelization, Lasse Natvig and Alexandru Iordan, in CEPIS Upgrade magazine, special Issue on Green ICT, november 2011. CEPIS paper, PDF (Lightweight introductory paper)
  4. Amdahl's Law in the Multicore Era, M.D. Hill, M.R. Marty, Computer, July 2008 (ITSL = Made available to students thru Its Learning)
  5. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, Kumar et.al. MICRO 2003 (ITSL)
  6. Models and metrics to enable energy-efficiency optimizations, Suzanne Rivoire et.al., Computer, December 2007 (ITSL)
  7. Real Time Power Estimation and Thread Scheduling via Performance Counters, Karan Singh, Major Bhadauria, Sally A. McKee, ACM SIGARCH Computer Architecture News archive, May 2009 (ITSL)
  8. Decomposable and Responsive Power Models for Multi-core Processors using Performance Counters, ICS'10, Ramon Bertran et.al., June 2010. (ITSL)
  9. Complete System Power Estimation Using Processor Performance Events, Bircher and John, IEEE Trans on comput, April 2012 (ITSL)
  10. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU, Lee et.al., ISCA 2010 (ITSL)
  11. Introduction to the wire-speed processor and architecture H. Franke et.al., IBM J. RES. & DEV, Jan/Feb 2010 paper, (ITSL)
  12. Feedback-Driven Threading: Power-Efficient and High-Performance Execution of Multithreaded Workloads on CMPs , Suleman et.al., ASPLOS'08 (ITSL)
  13. Case Studies of Multi-core Energy Efficiency in Task Based Programs, Hallgeir Lien et al, In proc. of ICT-GLOW — ICT againts Global Warming, Vienna Sept 2012 (ITSL)
  14. Memory-Link Compression Schemes: A Value Locality Perspective, Martin Thuresson et.al., IEEE Transactions on Computers, July 2008 (ITSL)
  15. collection of slides from Int'l seminar at 3. October, see note above, and see its'learning.



2014/09/15 19:33, Lasse Natvig