NTNU IME IDI

TDT1 - Multicore architectures and chip multiprocessors
(Flerkjerneprosessorer)

 Responsible: Lasse Natvig

TDT1 has got a new webpage from 2009, please go to
http://www.idi.ntnu.no/emner/tdt4260/tdt1

(Reading list of last years course is found below)

Pensum 2008:

  1. 11/9: Oppstartsmøte avholdt. Vi ble enige om å bruke Tirsdag 1315-1500 og Onsdager 1015-1200 som "aktuelle tidsluker". Nærmere tid og sted annonseres her.
  2. Uken 15 - 19/9: The HiPEAC Roadmap document, Self-study.
  3. 24/9: The What, Why, and How of MPSoC's, Chap. 1 in Multiprocessor Systems-on-Chips, Jerraya & Wolf. Responsible: Lasse | slides (The chapter is included to give a coarse overview of and to explain the "border" to another but related topic).
  4. 30/9: Feedback Directed Prefetch Scheduling in CMPs, Marius Grannæs, Magnus Jahre and Lasse Natvig, to appear in Proceedings of ICCD-2008. Marius presenterer arbeidet. Artikkel sendt ut på mail. Slides
  5. 1/10: Dynamic Communication Models in Embedded System Co-Simulation, K. Hines og G. Borriello, proceedings 34'th Design Automation Conference, Anaheim June 97, side 395-400.
  6. 14/10: Memory-Link Compression Schemes: A Value Locality Perspective, Martin Thuresson, Lawrence Spracklen, and Per Stenstrom, IEEE Transactions on Computers, Volume 57, Issue 7, 2008 Page(s):916 - 927.
  7. 15/10: Scalable Value-Cache Based Compression Schemes for Multiprocessors, Martin Thuresson and Per Stenstrom, 18th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'06), Ouro Preto, Brazil, Oct 2006.
  8. 28/10: (When) Will CMPs hit the Power Wall? Technical Report.
  9. 29/10: A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors , Magnus Jahre & Lasse Natvig, Submitted to Transactions on HIPEAC. Artikkel og presentasjon er sent ut via mail. Ansvarlig: Magnus
  10. 18/11 kl. 1315-1500(max) i rom 454: Larrabee: A Many-Core x86 Architecture for Visual Computing: Ansvarlig: Gjesteforelesning ved Terje Mathisen
  11. Evaluating the Imagine Stream Architecture, Jung Ho Ahn et.al., ISCA-2004. Ansvarlig: Selvstudium
  12. A Case for Intelligent RAM, David Patterson et.al., IEEE Micro 1997, and Overcoming the Limitations of Conventional Vector Processors, C. Kozyrakis and D. Patterson, ISCA 2003. Ansvarlig: Selvstudium



Course responsible: Lasse Natvig | Chip multiprocessing resources


Editor: Lasse Natvig  Contact address: http://www.idi.ntnu.no/~lasse/  Page updated:
2009-09-12