Magnus Jahre's homepage
Associate Professor Dept. of Computer and Information Science (IDI) Faculty of Information Technology, Mathematics and Electrical Engineering (IME) Norwegian University of Science and Technology (NTNU) Gløshaugen, N-7491 Trondheim, Norway Office: Room 404, IT-building (See IDI on this map) E-mail: magnus.jahre at idi dot ntnu dot no Phone: +47 735 93680 Fax: +47 735 94466 Mail address: Magnus Jahre, IDI, Sem Særlands vei 7-9, NO-7491 Trondheim, Norway
Research Main research focus: Resource sharing- and utilization techniques for Chip Multiprocessor (CMP) Memory Systems Publications 2011 Marius Grannaes, Magnus Jahre and Lasse Natvig Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strategy Architecture of Computing Systems (ARCS) Marius Grannaes, Magnus Jahre and Lasse Natvig Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables Journal of Instruction Level Parallelism, Volume 13 2010 Magnus Jahre Managing Shared Resources in Chip Multiprocessor Memory Systems PhD Thesis, NTNU Marius Grannaes, Magnus Jahre and Lasse Natvig Multi-Level Hardware Prefetching using Low Complexity Delta Correlating Prediction Tables with Partial Matching Transactions on High-Performance Embedded Architectures and Compilers, Volume 5, Issue 1 Magnus Jahre, Marius Grannaes and Lasse Natvig DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems The 5th International Conference on High Performance and Embedded Architectures and Compilers Marius Grannaes, Magnus Jahre and Lasse Natvig Multi-Level Hardware Prefetching using Low Complexity Delta Correlating Prediction Tables with Partial Matching The 5th International Conference on High Performance and Embedded Architectures and Compilers 2009 Magnus Jahre, Marius Grannas and Lasse Natvig A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures 11th IEEE International Conference on High Performance Computing and Communications (HPCC) Magnus Jahre and Lasse Natvig A Light-Weight Fairness Mechanism for Chip Multiprocessor Memory Systems ACM International Conference on Computing Frontiers Magnus Jahre and Lasse Natvig A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors Transactions on High-Performance Embedded Architectures and Compilers Volume 4, Issue 1 Marius Grannaes, Magnus Jahre and Lasse Natvig Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables 1st JILP Data Prefetching Championship Guttorm Sindre, Lasse Natvig and Magnus Jahre Experimental Validation of the Learning Effect for a Pedagogical Game on Computer Fundamentals IEEE Transactions on Education 2008 Marius Grannaes, Magnus Jahre and Lasse Natvig Low-Cost Open-Page Prefetch Scheduling in Chip Multiprocessors XXVI IEEE International Conference on Computer Design (ICCD) 2007 Magnus Jahre and Lasse Natvig Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor Norwegian Informatics Conference Magnus Jahre Improving the Performance of Parallel Applications in Chip Multiprocessors with Architectural Techniques Master Thesis, NTNU 2006 Magnus Jahre Interprocessor Communication in Chip Multiprocessors Project Report in TDT4720 Computer Design and Architecture, Specialisation The Integrated PhD Program at IDI/IME My PhD education followed the Integrated PhD Program at IDI. In essence, this means that the first two years of my PhD overlaped with the last year of my master. During these two years, half of my time on was used on my master and half on research. The main advantage of this program is that the master thesis is focused on problems that are highly relevant for the PhD. Consequently, when the master thesis is finished, you are ready to do real research. If you want more information about the Integrated PhD program, you can check out the official web pages (in Norwegian) or send me an e-mail. Errata Performance Effects of a Cache Miss Handling Architecture in a Multi-core Processor: In figure 5a and 5b, "Miss Status" should be MSHR and "Targets" should be "Write Buffer". Figure 5c is a bit unclear. Here, the write buffer has the size of one cache line. However, a more precise heading would be "Write Buffer" rather than "Cache Line". In table 2 on page 8, the size of both the L1 data cache and L1 instruction cache is 64KB and not 32KB. In addition, the block size in all caches are 64B and not 64KB. Master Thesis: In table 3.2 on page 51 there are some errors. Firstly, the size of both the L1 data cache and L1 instruction cache is 64KB and not 32KB. Secondly, the block size in all caches are 64B and not 64KB. Due to a bug in the simulator, the effective cache space available in each L2 bank is 256KB and not 1MB for the experiments using the SPLASH-2 benchmarks. Consequently, the total L2 cache space for these benchmarks is 1MB and not 4MB. Teaching Autumn 2005: Development, maintenance and day-to-day operation of the Age of Computers teaching system Spring 2006: Further development of the Age of Computers teaching system Autumn 2006: Teaching assistant, TDT4160 Computer Fundamentals Spring 2007: Teaching assistant, TDT4260 Computer Architecture Autumn 2007: Teaching assistant, TDT4160 Computer Fundamentals Spring 2008: Teaching assistant, TDT4260 Computer Architecture Autumn 2008: Assistance to new teaching assistants in the DM-group Spring 2009: Teaching assistant, TDT4260 Computer Architecture Spring 2010: Teaching assistant/Part time lecturer, TDT4260 Computer Architecture Autumn 2010: Lecturer, TDT4160 Computer Fundamentals Autumn 2010: Coordinator, TDT4295 Computer Design Project Spring 2011: Lecturer, TDT4258 Microcontroller System Design