Several different computer architectures that will fit with the BSP model are proposed. Communication- and synchronization algorithms for these architectures are also included.
A simulator for some of these computer architectures is made, supporting these architectures: network of workstations, distributed shared memory, and tightly coupled multiprocessor. All architectures are configurable, i.e. topology, network parameters, and size. The simulator supports logging of behavior, e.g. time spent for each processor on barrier synchronization or data received by a processor.
The simulator can be used as a tool for making BSP programs. It gives the user the opportunity to test the BSP program for different computer architectures, e.g. the user can check how well the BSP program scales with respect to number of processors. The simulator can be extended with new architectures, and in this way it can be used as a tool for testing the behavior of specific computer architectures as well. Some examples describe how new architectures can be made.
For extensions and modification of the simulator, there exists documentation at two levels (overall design and specific design).
Some results from testing of the simulator are included in this document. Suggestions of future extensions are also included.
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