NTNU IME IDI

DT8105 - PhD course Computer Architecture II

NTNU Computer Architecture Research Group       Course responsible: Lasse Natvig

See the new course web page for the spring term 2009.

Course contents spring term 2007: (This is a copy from our course intranet (ITSL). Links and slides not available here)

  1. Interconnections in Multi-core Architectures: Understanding Mechanisms, Overheads and Scaling, Rakesh Kumar, Victor Zyuban, Dean M. Tullsen, ISCA-2005. Responsible: Magnus | slides
  2. Evaluating the Imagine Stream Architecture, Jung Ho Ahn et.al., ISCA-2004. Responsible: Nico | slides
  3. Algorithms for scalable synchronization on shared-memory multiprocessors, Mellor-Crummey, J. M. and Scott, M. L. ACM Transactions on Computing Systems, Feb. 1991, pages 21-65. Responsible: Jan Chr. | slides
  4. Exploring the Design Space of Future CMPs, J. Huh, D. Burger, and S. W. Keckler, 10th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT'01), pages 199-210. Responsible: Lasse. | slides
  5. Guest lecture by Trond R. Hagen on GPU HW and SW (Partly based on An Introduction to General-Purpose Computing on Programmable Graphics Hardware, Tor Dokken, Trond Runar Hagen, and Jon Mikkelsen Hjelmervik, SINTEF, 2007, preprint, 37 pages. (Only pages 1-24 (section 1-5) are included). | slides
  6. Guest lecture by Haakon Dybdahl (Google, Trondheim), Introduction to cache + An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors, H. Dybdahl and P. Stenström, in Proc. of HPCA-13 and
  7. A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors, H. Dybdahl, P. Stenström and L. Natvig, HiPC 2006 (Best paper award).
  8. Self-study: Picking Statistically Valid and Early Simulation Points, Erez Perelman, Greg Hamerly and Brad Calder, PACT-2003
  9. Self-study: The Stanford FLASH Multiprocessor, Jeffrey Kuskin et.al. In Proceedings of the 21st International Symposium on Computer Architecture, pages 302-313, Chicago, IL, April 1994, (Old slides from Lasse), supplemented by
  10. Retrospective: The Stanford FLASH Multiprocessor, Jeffrey S. Kuskin, Retrospective in 25 Years of the International Symposia on Computer Architecture - Selected Papers. pp 95-97.
  11. Self-study: Architecture of a Massively Parallel Processor, Kenneth E. Batcher, In proceedings of 7th International Symposium on Computer Architecture, 1980, supplemented by
  12. Retrospective: Architecture of a Massively Parallel Processor, Kenneth E. Batcher, in Retrospective in 25 Years of the International Symposia on Computer Architecture - Selected Papers. pp 15-16
  13. Self-study: Cell Moves Into the Limelight (only available as paper copy) K. Krewell, Microprocessor report, february 2005. And supported by ...
  14. Power Efficient Processor Architecture and The Cell Processor, H.P. Hofstee, from HPCA-2005.
  15. Self-study: A Case for Intelligent RAM, David Patterson et.al., IEEE Micro 1997, and

  16. Overcoming the Limitations of Conventional Vector Processors, C. Kozyrakis and D. Patterson, ISCA 2003.

  17. Self-study: The CM-5 Connection Machine: A Scalable Supercomputer, W. Daniel Hillis and Lewis W. Tucker, CACM Vol. 36, No. 11, Nov 1993, page 31-40

Links: Lasse Natvig | Course web page from 2003 | WWW-CoArch | Chip multiprocessing resources |


Editor: Lasse Natvig  Contact address: http://www.idi.ntnu.no/~lasse/  Page updated:
2009-04-14