Round Corner
Department of Computer and Information Science


A RISC V Oberon compiler backend

Current software systems require multiple gigabytes of memory and multicore systems to run efficiently. However, the advances in hardware speed and capabilities due to the advancement of Moore's Law that enabled this so-called "software bloat" are coming to an end. Accordingly, a movement advocating for lean software has surfaced [1]. This is based on the observations that earlier computers were able to provide a useful working environment including a graphical user interface and networking with far fewer resources.

One system demonstrating the possibility of creating such a lean system is Niklaus Wirth's Project Oberon system [2]. Using a self-designed programming language, Oberon, and his own RISC processor implemented on a tiny FPGA, Wirth was able to create a system including a graphical user interface, networking, and a compiler running on a 25 MHz CPU in 1 MB of RAM. The complete system is open source, including the hardware and compiler, the source code for hard- and software can be read by a single person on a rainy weekend.

Your task will be to support the analysis if a reduced resource system can also be efficiently implemented using a RISC V CPU core [4]. RISC V is an open source specification that has enabled a large number of implementations ranging from small embedded cores to high-performance 64-bit multicores. The first step enable this is to adapt the Oberon compiler backend to generate RISC V code instead of code for Wirth's RISC machine. In addition, you will extend an open source Project Oberon simulator system [5] to support a RISC V CPU, which will enable you to test your compiler output. Optionally, a hardware implementation on an FPGA based on an open source RISC V core is possible.

Useful prerequisites for working on this project are experience with assembler programming and computer architecture, and basics of compilers and code generation. Experience with C/C++ programming (for extending the simulator) or hardware design (for creating the FPGA system) is useful.

[1] N. Wirth, Project Oberon (2013 Edition), available online:

[2] N. Wirth, A Plea for Lean Software, in Computer, vol. 28, no. 02, pp. 64-68, 1995.

[3] Niklaus Wirth. 1996. Compiler construction. Addison Wesley Longman Publishing Co., Inc., USA. Updated 2017 edition available online:

[4] David Patterson, Andrew Waterman, The RISC-V Reader: An Open Architecture Atlas, 2017, ISBN 9780999249116

[5] Peter de Watcher, Oberon RISC Emulator:


Michael Engel Michael Engel
Associate Professor
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