Comp.arch II (DT8105) Spring 2009 - final reading list

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Note: (a) Some of the links may require a NTNU-Innsida login. (b) It is only the paper that is the official part of the reading list, in cases where slides are given there is no guarantee that the slides are entirely correct or that they represent the paper in a complete or correct manner.

  1. Memory-Link Compression Schemes: A Value Locality Perspective, Martin Thuresson, Lawrence Spracklen, and Per Stenstrom, IEEE Transactions on Computers, Volume 57, Issue 7, 2008 Page(s):916 - 927.
  2. (When) Will CMPs hit the Power Wall? Technical Report CE-TR-2008-04, Cor Meenderinck and Ben Juurlink, Computer Engineering Department, Delft University of Technology, 2008. Slides from the authors.
  3. Rise of the Graphics Processor, Blythe, D., 2008. (Available through It's learning) LN-slides from TDT4260.
  4. Larrabee: A Many-Core x86 Architecture for Visual Computing, ACM Transactions on Graphics, Vol. 27, No. 3, Article 18, August 2008.
  5. Evaluating the Imagine Stream Architecture, Jung Ho Ahn, ISCA-2004. SJ-slides
  6. Exploring the Design Space of Future CMPs, J. Huh, D. Burger, and S. W. Keckler, 10th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT'01), pages 199-210. LN-slides
  7. A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors, H. Dybdahl, P. Stenström and L. Natvig, HiPC 2006 (Best paper award).
  8. TFlux: A Portable Platform for Data-Driven Multithreading on Commodity Multicore Systems, Stavrou, K., Parallel Processing, ICPP, 9-12 Sept. 2008, pages 25-34.
  9. CellSs: making it easier to program the cell broadband engine processor, J. P. Perez, P. Bellens, R. M. Badia, J. Labarta, September 2007, IBM Journal of Research and Development, Volume 51, Issue 5. (Available through It's learning) ME-slides
  10. Latency Impact on Spin-Lock Algorithms for Modern Shared Memory Multiprocessors, Jan Christian Meyer and Anne C. Elster, in Scalable Computing: Practice and Experience, Volume 9, Number 3, pp. 197–206, (September 2008). JCM-slides
  11. Storage Efficient Hardware Prefetching using Delta Correlating Prediction Tables, Marius Grannaes, Magnus Jahre and Lasse Natvig. Presented at 1st JILP Data Prefetching Championship, 2009. Presentation, All details, IDI-news

2009/06/08 22:52, Lasse Natvig