Year 2009 edition of TDT1 multicore architectures and chip multiprocessors

Students: Georgy U., Ulf L., Odd Rune L., Magne R., Tor Arne L., Jon Tore H, Kjetil WO, Martin T.

TDT1 is a specialist 5th year course on multicore architectures and chip multiprocessors. Below is the final selection of course material (reading list). The first meeting was held 11/9-2009. The course will focus on having an up to date reading list of high quality, but with relatively few meetings. These will be held as colloquia with presentations given by the students and the teacher. We agreed on Mondays 12-14 and Thursdays 10-16 as suitable timeslots.

Note that the exam will be Friday 27/11 although it will be the day before for most other courses of this kind.

Questions can be addressed to Lasse Natvig, preferably by E-mail.

Final reading list and meeting-schedule 2009: (Note that Innsida-login at NTNU or through VPN might be required for some of the documents). Some dates might be changed.:

  1. HiPEAC RoadMap 17/9. Responsible: Odd Rune Lykkebø | slides.
  2. Roofline: an insightful visual performance model for multicore architectures, Communications of the ACM, Vol. 52, April 2009, pages 65-76. 21/9. Responsible: Ulf Lilleengen | slides.
  3. Memory-Link Compression Schemes: A Value Locality Perspective, Martin Thuresson, Lawrence Spracklen, and Per Stenstrom, IEEE Transactions on Computers, Volume 57, Issue 7, 2008 Pages 916 - 927. 1/10. Responsible: Georgy Ushakov | slides
  4. Larrabee: A Many-Core x86 Architecture for Visual Computing, Larry Seiler, ACM Transactions on Graphics, Vol. 27, No. 3, August 2008. 8/10. Responsible: Tor Arne Lye. slides
  5. Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures, Jahre, M., Grannaes, M. and Natvig, L., In proceedings of High Performance Computing and Communications (HPCC), June 2009. HPCC '09. 12/10. Responsible: Magnus Jahre slides .
  6. (When) Will CMPs hit the Power Wall?, Cor Meenderinck and Ben Juurlink, Technical Report TUDelft, 2008. 19/10 Responsible: Magnus Romnes slides.
  7. Joint Compiler/Hardware Exploration for Fair Comparison of Architectures, Veerle Desmet, Sylvain Girbal, and Olivier Temam; INTERACT-13, Workshop on Interaction Between Compilers and Computer Architecture, held in conjunction with HPCA-15, February 15, 2009. (Available to students through NTNU-ITSL). 5/11. Responsible: Jon Tore Hafstad slides
  8. PIPP: Promotion/Insertion Pseudo-Partitioning of Multi-Core Shared Caches, Yuejian Xie, Gabriel H. Loh, ISCA-2009. (Available to students through NTNU-ITSL) 12/11. Responsible: Kjetil Oftedal slides
  9. Spending Moore's Dividend, Larus, James, Communications of the ACM (CACM), vol. 52, May 2009, pages 62-69. Self study.

Previous editions of the course: 2008-edition

2010/08/30 15:00, Lasse Natvig