Evolvable Hardware Group
Technologies for Evolvable Hardware

Introduction       Participants       Current Projects     Relevant Publications

The main focus of the research community has mainly been directed towards traditional technology platforms and applying evolutionary techniques to these platforms to evolve new and hopefully better designs and thus prove the worth of evolvable hardware as a design technique. However, can we really realise the opportunities that lie in design by evolution by using traditional technologies or are there better technologies which will allow us to fully realise the potential inherent in evolvable hardware?

We believe that this is the case. Whether we should be looking at improving electronics turning to newer technologies through studying possiblities within chemistry, biology or physics is hard to say. Our key focus in this area is to study different possible technologies and compare their features with the requirements for Evolvable Hardware to pick out key technologies for further investigation.

An interesting introduction to this area was given by Julian Miller at Evolvable Hardware 2000. In his invited talk he suggested that perhaps in the future instead of talking about FPAA's (for analogue) or FPGA's (for digital) we will be looking at FPMA's - full programmable matter arrays. This is an important concept for this field.



Pauline Haddow, Assoc. Professor, Department of Computer and Information Science, NTNU

Morten Hartmann, PhD student, Department of Computer and Information Science, NTNU
Gunnar Tufte, PhD student; Department of Computer and Information Science, NTNU


Current Projects

An Evolvable Hardware FPGA
In this work we consider the characteristics of evolvable hardware --- especially for adaptive design, and discuss the demands that these characteristics place on the underlying technology. We suggest a potential alternative to today's FPGA technology. The proposed architecture is particularly focused at reducing the genotype required for a given design by reducing the configuration data required for unused routing resources and allowing partial configuration down to a single CLB. In addition, to support adaptive hardware, self-reconfiguration is enabled.

We will shortly be testing out our design on a more standard FPGA, that is developing a virtual new FPGA on top of a traditional FPGA.

Future Technololgies

Investigation into possible future technologies is at an early stage. Part of this work will be conducted jointly with Julian Miller at the University of Birmingham.


Relevant Publications

[main  EHW page]

Norwegian University of Science and Technology  NTNU
Faculty of Physics, Informatics and Mathematics  FIM                                                                    Design and maintainance: Pauline Haddow
Department of Computer and Information Science  IDI                                                                            Last update: Tuesday, 8-Aug-2000