Evolvable Hardware Group
Complete Hardware Evolution (CHE)

Introduction           Participants        Implementation         Current Projects     Relevant Publications

The application of evolutionary techniques to hardware design is termed evolvable hardware. The main goal being to
replace traditional design methods with evolutionary techniques for given applications which are either not achievable using traditional methods or which benefit from an evolutionary approach.

Extrinsic evolution uses a software simulation of the underlying hardware to evaluate the fitness value of each individual. This may be an advantage if you do not wish to be too technology specific such that the model of the hardware may be quite abstract. On the other hand if technology is the goal then more accurate fitness values may be obtained from an actual implementation than those obtained through an abstraction of the underlying technology i.e. a simulation. Since fitness steers the selection process and thus evolution, then abstracting from technology can lead to a less optimal solution.

In Intrinsic evolution fitness evaluation, is based on a hardware implementation where each individual is implemented and evaluated on the target technology. This approach can be used to explore properties of the technology which can not be utilised using traditional design methods. The evolution process runs on a host computer responsible for selection and the  performance of genetic operators. Each individual is down-loaded to the chip as configuration data --- design descriptions. Fitness evaluation of a given individual is achieved by applying test vectors to the implemented individual and then calculating the fitness value from the response.

In Complete Hardware Evolution (CHE) the genetic algorithm (GA) is implemented on the same chip as the evolving design.  The GA implementation configures the evolving design by placing individuals in Random Access Memory (RAM). The fitness value is calculated by the GA from the feedback signals originating in the evolving design. Since the GA and the evolving design are implemented on the same chip, the evolution process may continuously observe the evolving design.

If a CHE design which meets specified goals is created and the evolution process is designed to be triggered by changes in the surrounding hardware or the environment so as to restart evolution, then CHE may offer a flexible adaptive hardware design  process. This is one of the goals of CHE. Since the evaluation of how well the proposed design solves the specified task is done by the fitness evaluation, exploration of a new design proposal could be started up when the current design no longer solves it's task satisfactorily. Using CHE, where the evolution process is on the same chip, adaption does not need to be decided at design time but the required change in the circuit is free to evolve dynamically with changing external factors.



Pauline Haddow, Assoc. Professor, Department of Computer and Information Science, NTNU

Gunnar Tufte, PhD student; Department of Computer and Information Science, NTNU

One of the main goals in the implementation phase of the GA Pipeline ( the GA implementation in CHE) was to achieve a flexible design which could easily be adapted, if necessary, to meet the requirements of different evolvable designs. The nature of the pipeline is, in itself, a flexible structure providing a modular design where modules may be replaced or additional modules added where required. To make the design flexible with respect to the implementation technology, the goal was to implement all the modules in VHDL such that the design could be synthesised in the technology of choice. The choice of VHDL for the logic and control blocks makes these blocks flexible with respect to design changes. Simple changes like changing the genetic operator parameters may be achieved through a change to the respective parameter in the genetic operator module and re-synthesis of the module design. Other changes may require more fundamental adaption of the code such as changing the sorting algorithm in SG.

Current Projects

The CHE method is applied to most of the work in the group. As such, we refer the reader to the other sections in our research section for associated projects.
CHE on Xilinx Virtex

Our current implementation of the GA pipeline and the CHE implementation itself may be synthesised into different technologies. However, the newer Virtex series from Xilinx offers newer features which if utilised may enable a more efficient design to be realised. In addition, our original GA pipeline design was designed with a focus on flexibility but with little focus on efficiency.  Therefore, we are currently  redesigning the GA pipeline to achieve a more effecient Virtex based design.


Relevant Publications

"Prototyping a GA Pipeline for Complete Hardware Evolution", abstract, postscript
by Gunnar Tufte and Pauline Haddow,  EH'99, pp 143-150
[main  EHW page]

Norwegian University of Science and Technology  NTNU
Faculty of Physics, Informatics and Mathematics  FIM                                                                    Design and maintainance: Pauline Haddow
Department of Computer and Information Science  IDI                                                                            Last update: Friday, 4-Aug-2000